TND

Fields	Goals	Research Results
Tera- level Nanoelectronics	Tera-level Single Electron Memory (SEM), 30nm-level CMOS and Ultra High Speed IC Unit Device Design and Fabrication	- Fabrication of Tera-level(30nm) SONOS Memory Devices (World’s First) - Demonstration of 50m-level Single Gate and 40nm-level Double Gate CMOS (World’s First) - Development of SET Logic Circuit on Chip (World’s Best) - Fabrication of InGaAs Nano-HEMT (fT=421GHz, Lg=30nm)
Spintronics	Fabrication of Spin/Electron Hybrid Device and Material Development (MR ratio>40%)	- Fabrication of 0.32μm2 MTJ (MR ratio>40%) - Fabrication of MTJ (Junction Area : 0.02μm2, Smallist in the World)
Molecular electronics	Fabrication of Tera-level Unit Device (25˚C Transistor)	- Demonstration of Vertical CNT Transistor (30˚K) and Non-volatile Memory (World’s First)
Core technologies	Development of 50nm-level Core Tech. and Basic Nano-analysis	- Development of Neutral Beam Source for Damage-free Etching Process (World’s First) - 100 Times Improvement of Litho. Speed (2mm/sec) using New Resist (World’s Best) - Development of AIPEL(Atomic Image Projection Electron-beam Lithography) – Quantum Dots/Wires Formation Litho. Equipment

■ Patents(Resistered) : Domestic 162(12), International 120 (6)
■ Papers(SCI) : Domestic 77(46), Internationalc 198( 192)
■ Conference(Invited Talks) : Domestic 322(30), International 332(56)

Fields	Goals	Research Results
Tera-level Nanoelectronics	Tera-level NVRAM, Nano CMOS, SET, CNT Devices and RT-based Ultra High Speed IC Integrating Technologies	- Overcoming the Integration Limit of NAND Flash by Development of MANOS Structure - Development of Analysis Method for Oxide Film(sub-1.5nm) Formed on Nano Device (World’s First) - Development of 77 ˚K Si-SET and 5nm-level Nano Patterning - Development of 25nm InGaAs Nano HEMT (f_T =511GHz) - Technology Transfer of 100nm-level HEMT & MMIC Technology (KANC) - Development of High Purity SWNT Synthesis at Room Temperature (World’s First) - Development of Separation Technology for Semiconducting CNT (World’s Best)
Resistive-RAM	Development of 256M-level MRAM Integrating Technologies	- Development of New Material for MRAM
Core technologies	Development of 25nm-level Core Technologies	- Development of World Best CNT Probe for AFM Lithography - Development of Atomic Layer Etching Technology using the Neutral Beam (World’s First) - Development of RPALD Technology for Tera-level Nanodevices (World’s First) - Fabrication of Quantum Dot/Wire with ~20nm-level Feature Size by AIPEL System - Development of High Speed Optical Interconnection Platform Based on Optical PCB (World’s First)

■ Patents(Resisterd) : Domestic 245(121), International 231(75)
■ Papers(SCI) : Domestic 54(31), International 307(300)
■ Conference(Invited Talks) : Domestic 259(37), International 399(75)

Fields	Research Goals
Tera- level Nanoelectronics	- Development of Si-based 20nm-level Nonvolatile Memory - Development of 300 K Si-SET/FET Multi-functional Logic Device - Development of 10 nm Ultra High Speed Nano-HEMT Devices ( >700GHz) - Development of Carbon Nanotube Electronic Devices TEG
Magnetoelectronics	- Development of Ultra High Density Magneto-electronic Devices
Core technologies	- Development of High Speed AFM Lithography System - Development of Neutral Beam Etching Equipments and Processes for 300 mm Wafer - Development of Plasma ALD Technology for Nanodevices - Development of 20 nm-level Quantum Dot/Wire Formation using AIPEL

■ Patents(Resisterd) : Domestic 287(320), International 225(137)
■ Papers(SCI) : Domestic 48(32), International 345(337)
■ Conference(Invited Talks) : Domestic 241(28), International 569(62)